The present invention relates generally to a dynamic random access memory (DRAM) device and, more particularly, to a DRAM device having an annular signal transfer region.
In the semiconductor industry, there is an ever-increasing desire to increase memory density and performance. These goals are often achieved by scaling dynamic random access memory (DRAM) devices to smaller dimensions and operating voltages.
A DRAM cell may include a horizontal, planar, MOSFET (metal oxide semiconductor field effect transistor) coupled to a deep trench storage capacitor by a buried strap. Such a DRAM cell may occupy a substrate surface area of 8F2 (where F is a minimum lithographic dimension) and may include a trench capacitor having a 1Fxc3x972F cross section. As the surface area of the 8F2 DRAM cell is reduced to 7F2, the cross section of the trench capacitor is typically reduced to 1Fxc3x971F. Compared to the 8F2 design (e.g., a merged-isolation and node-in-trench, or MINT, design), the 7F2 design is more susceptible to large threshold voltage (Vt) variations mainly due to GC-DT (gate conductor-deep trench) overlay tolerance.
In the above example, there is a factor of two reduction in trench cross-section area. There may be an additional factor of two decrease resulting from the generation-to-generation ground rule scaling. For example, when the generation-to-generation ground rule scaling reduces the minimum feature size by a factor of 0.7, the 1Fxc3x972F=2F2 trench capacitor is first reduced to 1Fxc3x971F=1F2 and then further reduced to 0.7Fxc3x970.7F=0.49F2. Such scaling may result in reduced storage capacitance, reduced operating voltages, non-scalability of the threshold voltage (Vt), and large Vt variations. The compounded effects of these factors may cause a decrease in sensing reliability and immunity to noise and soft errors.
The reduction in storage capacitance is directly caused by the scaling of the DRAM cell to a smaller dimension because a smaller capacitor can store less charge. In addition, storage capacitance is also reduced because capacitor node dielectric thickness may not be proportionately scaled due to reliability considerations.
Vertical memory devices have been proposed to increase memory density without reducing storage capacitance. A vertical memory device may be formed by having a signal storage node and a signal transfer device formed in a trench. FIG. 1 illustrates a vertical memory device 100 formed in a trench within a substrate 10 as disclosed by Kimura et al. in U.S. Pat. No. 5,177,576.
The signal storage node of the memory device 100 shown in FIG. 1 has both a first electrode and a second electrode formed within the trench. The first electrode 11 is bound by insulating layers 9 and 14. The second electrode 15 is formed on the interior side of insulating layer 14. The first electrode 11 is coupled to the first electrode of other devices by diffusion layer 12.
The second electrode 15 of the signal storage node is coupled to the bit lines 20, 28 by a signal transfer device. The signal transfer device includes diffusion regions 23, 24 and a channel area 22. The channel area 22 is bound by an insulation film 19 along the side wall of the trench and by an insulating layer 25 on the interior side of the trench. The channel area 22 of the memory device 100 in FIG. 1 is controlled by the word line 30 which is coupled to the gate electrode 26. The bottom of the gate electrode 26 is isolated from the signal storage node by an insulator 251.
The memory device 100 illustrated in FIG. 1 may not be operable for long retention-time DRAM applications due to floating-body (floating-channel) effects. Floating body effects are recognized in silicon-on-insulator (SOI) technology as being highly detrimental for long retention-time DRAM applications. Although the memory device 100 in FIG. 1 does not use SOI technology, the geometry of the cell results in a design which is analogous to a floating body in SOI technology because the channel area 22 is not coupled to a voltage reference. For example, because the body-charge is isolated from the substrate 10, the body-charge in the channel area 22 may vary depending on the operating history of the signal transfer device. This arrangement may result in dynamic charge leakage from the signal storage node which may prevent reliable operation of memory device 100 for long retention-time applications.
To overcome the shortcomings of conventional DRAM devices, a new DRAM device is provided. An object of the present invention is to provide a DRAM device that has improved charge retention characteristics. A related object is to provide a process of manufacturing such a DRAM device. Another object is to provide a DRAM device that occupies a reduced semiconductor surface area while maintaining sufficient storage node capacitance. Another object is to provide a DRAM device having a signal transfer device with a large width-to-length ratio. It is still another object to provide a DRAM device having a signal transfer device with an annular signal transfer region. Yet another object is to provide a DRAM device having a bit line conductor elevated above the word lines. Another object of the present invention is to provide a DRAM device capable of fully depleted operation for near ideal sub-Vt slope and near zero substrate sensitivity.
To achieve these and other objects, and in view of its purposes, the present invention provides a memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, and a node dielectric formed between the first and second electrodes. A signal transfer device has: (i) an annular signal transfer region with an outer surface adjacent the side walls of the trench, an inner surface, a first end, and a second end; (ii) a first diffusion region coupling the first end of the signal transfer region to the second electrode of the signal storage node; (iii) a second diffusion region coupling the second end of the signal transfer region to the bit line conductor; (iv) a gate insulator coating the inner surface of the signal transfer region; and (v) a gate conductor coating the gate insulator and coupled to the word line. A conductive coupling member couples a portion of the outer surface of the signal transfer region to a reference potential.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.